IC Knowledge - IC Cost Model

Introduction
The IC Knowledge - IC Cost Model is designed to enable users to easily estimate manufacturing costs for most IC's. The cost model runs inside of Excel, the user makes selections from drop-down menus on 2 worksheets covering wafer and product cost. The user must make 7 selections many of which have lookup help available, there are 66 additional selections available on the default sheet that may be overriden if desired to fine tune the model and the process may now be fined tuned to add and subtract individual process steps. All of the defaults are technology specific and in most cases will not need to be changed. There are 8 output sheets that provide a detailed breakout of costs. The model also includes a calculator for stacked die - multi-chip packages.

Who should buy this product

This product is designed to serve the needs of anyone interested in understanding the manufacturing costs of integrated circuits and who also wants detail on the wafer fabrication costs section.
Do you:

Purchase ICs and want to know what it really costs your supplier to make the ICs?
Market ICs and want to know what your competitors products cost?
Market equipment and want to understand how equipment costs impact IC costs?
Manage an IC manufacturing operation and want to benchmark your company against others?
Follow IC companies stocks and want to know what particular products cost them to make?
Develop new products and want to understand the cost impact of process decisions.
Work at a Fabless IC company and want to know what it costs your suppliers to make wafers for you?

If you answered yes to any of the question above, then this product is for you.

What is different for 2009 versus the 2008 model
For the 2008 model all of the underlying model data has been reviewed and in many cases updated. Specifically direct and indirect labor rates, electricity and natural gas and starting wafer costs have been updated. The 2009 model also has several new processes more new processes planned to be added as the year progresses.

How to get more information about the model
We provide several tools to better understand the model before purchasing it.

Email us to get a demo copy of the model.
Applications notes detail the processes and packages supported, there are also several applications notes from the 2001 and 2002 models that although the model has changed and they don't specifically apply are still useful in a general sense. Application notes may be down loaded from the support page.
Process and package type lists.

If none of these tools answers your questions, please feel free to E-mail us at info@icknowledge.com

Revision history

The following is the revision history for the 2009 IC Cost Model:

Revision 0900 - Updated material costs, DL and IDL rates. Added new die sizes. Updated electric and natural gas prices. Fixed a bug in user entered class test costs. Added: 300mm - 90nm - SMIC - dual gate oxide CMOS logic - 1 poly and 6 copper layers process. Added: 300mm - 40nm - TSMC - eDRAM - 9 through 11 copper layers processes. Added: 300mm - 45nm - IBM - eDRAM on SOI - 9 through 11 copper layers. Added: 300mm - 40nm - UMC - FPGA process with Flash - 11 copper layers. Added: 300mm - 40nm - Toshiba - FPGA process with Flash - 11 copper layers. Added product type display to '6 Cost summary' page. Added: 300mm - 32nm - TSMC - dual gate ox with High-k CMOS logic process - 9 through 11 copper layers. Added: 300mm - 32nm - IBM - eDRAM on SOI with dual High-k gate oxides - 9 through 11 copper layers. Added ASIC Product Type lookup to the '2 Wafer cost' sheet. Added: 300mm - Samsung - DRAM - 3 metal (1W + 2Al) process. Fixed an error in the upgrade calculations. Sheets 2, 3, 4, and 6 can now be copied for archival purposes.
Revision 0901 - updated very low volume package pricing. Added: 300mm - 65nm - Chartered - 7 and 8 metal layer processes. Added: 300mm - 32nm - TSMC - dual gate oxide CMOS logic process - 9 layer copper process. Added: 300mm - 28nm - TSMC - high-k CMOS - 9 through 11 layer copper processes. Added: 300mm - 22nm - TSMC - PROJECTED high-k CMOS - 9 through 11 layer copper processes. Adjusted 32nm foundry OEE. Adjusted 32nm processes high-k materials usage.
Revision 0901a - adjusted sheet '16 Summary' so it can be copied. Added: 300mm - 28nm - TSMC - eDRAM with high-k - 9 through 11 copper layers.
Revision 0902 - added more options for test times with greater granularity. Updated 100mm, 125mm and 150mm wafer prices. Added: 300mm - 130nm - ST MIcro - BiCMOS 9 - 7 layer copper with and without MIM. Added: 200mm - 250nm - TSMC - single gate oxide CMOS logic - 1 layer poly - 6 aluminum layers.
Revision 0903 - added new die sizes. Added six core microprocessor to product types. Added Fujitsu 130nm PLD process with 8 copper layers.
Revision 0904 - changed the model to be quarterly based instead of yearly based. Did a detailed review of production dates for all 300mm Fabs and processes and adjusted as required to insure accuracy under the quarterly model.

Cost and how to buy

1st copy price - $1,600
2nd or 3rd copy price - $1,067
4th copy - $853
Enterprise license - $5,440

You can order on-line or we accept purchase orders from most companies.

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