IC Knowledge - Glossary

Glossary of Integrated Circuit Terminology - L

Large Scale Integration - integrated circuits containing >1,000 but <100,000 transistors.
Latch Up - a condition that can occur in CMOS where Parasitic NPN and PNP Transistors are both Conducting and remain Conduction once the disturbance that started the Conduction is removed.
Lateral - a Transistor of any type where Conduction is along the top surface of the Semiconductor. Example are Lateral PNP, Lateral DMOS, Lateral SCR, etc.
Leadframe - the Metal frame that Semiconductors are attached to during the Package Assembly process. Typically a Leadframe is a long Metal frame with positions for multiple Chips. After the Chips are attached to the Leadframe tiny wire are used to connect the Chip Bond Pads to the frame and then the positions on the frame where Chips are located are encapsulated in epoxy. After Molding the encapsulated Chips are mechanically broken loose from the frame rails and the parts of the frame protruding from the Package become the Package leads.
Learning Cycle - a Learning Cycle is the analysis-corrective action formulation-corrective action implementation cycle needed to fix a Yield problem.
LED - see Light Emitting Diode
Light - electromagnetic radiation with a wavelength between 1millimeter and 10nanometers.
Light Emitting Diode - a diode junction formed by compound semiconductors that emits light when forward biased.
Line Yield - see Wafer Yield
Linewidth - the width of a line either printed on a wafer or an opaque feature on a mask or reticle.
Linear Array - an integrated circuit made up of circuit elements that are not yet connected. Typically a linear array is processed up to the metal layers. When a customer places an order, a specific metal mask is generated to connect the circuit elements into the customers specific circuit.
Lithography - the transfer of a pattern from medium to another, for example, transferring a pattern from a mask or reticle to a wafer.
LOCOS - LOCal Oxidation of Silicon - oxidation of selected areas of a silicon wafer by masking off the oxidation reaction from other regions. A thin uniform silicon dioxide, SiO₂, layer is initially formed and then a layer of silicon nitride, Si₃N₄, is deposited. The silicon nitride is photolithographically patterned and then a relatively thick silicon dioxide layer is grown in the openings in the silicon nitride. The silicon nitride blocks oxidation wherever silicon nitride is present. Following oxidation the silicon nitride layer is stripped off the wafer. The thin initial silicon dioxide layer is used to prevent stress from direct contact between silicon and silicon nitride. LOCOS is widely used to isolated MOSFETs with minimum linewidths >350nanometers.
Logic - a set of circuit elements that perform a function.
Low-k - a dielectric material with a dielectric constant less than the dielectric constant of silicon dioxide, k<4. The propagation delay of a signal through an interconnect layer is related to the resistance and capacitance of the conductor. Low-k dielectric materials surrounding the conductor reduce capacitance and propagation delay.
Low Pressure Chemical Vapor Deposition - chemical vapor deposition performed at a pressure below atmospheric pressure.
LPCVD - see Low Pressure Chemical Vapor Deposition
LSI - see Large Scale Integration.