Why profit versus utilization for a semiconductor company appears to be linear?
Recently we were asked why the relationship between pre tax profit and utilization in our “How does Fab utilization effect profitability?” post was so linear, after all Fab costs versus utilization are highly non linear and are the largest piece of the product cost for most semiconductors.
Upon further reflection what we have concluded is as follows:
Fab cost versus utilization is highly non linear. We did some modeling with the IC Knowledge – 2001 IC Cost Model of a Fab running a 130nm CMOS logic process on 200mm wafers. Once we had a cost versus utilization curve we did a curve fit and found that the relationship is given by, cost = 1708.4 multiplied by utilization raised to the –0.8632 power. If you plot this equation what you will see is a very rapid fall in cost with incresing utilization up until approximately 30%, and from 30% to around 90% the continuing decrease in costs with increasing utilization is fairly close to a straight line.
Costs such as packaging are frequently outsourced and are not volume sensitive enough to make a big difference. Test costs have a high fixed cost component but are small compared to Fab costs. Below the line costs such as marketing and selling, research and development and general and administrative are all fairly linear.
Therefore what we believe is happening is the graph we presented only shows data above approximately 30% utilization and also has a fair amount of noise in the region of 50% to 80%, exactly where you expect to see curvature in the plot, so it appears linear
This discussion has triggered an idea for us. When we get the time we are going to look at extending the 2001 IC Cost Model out to model a whole company cost structure. It will be interesting to compare the result to the profit versus utilization figure. But for now we are fairly comfortable we understand why the figure "appears" linear.
