IC Knowledge - Mask Costs

Mask Cost Trends
The continual escalation in the cost of individual masks coupled with increasing process complexity has led to a crisis in mask set costs. According to SEMATECH data the average mask usage for ASIC, DRAM and Logic wafers is 500, 4,000 and 1,500 respectively. Using these numbers and calculating wafer costs with and without mask costs using the IC Knowledge - 2003 IC Cost Model we have calculated the percentage of wafer cost that mask costs represent for each case, see table 1.
250nm 130nm ASIC 32% 56% DRAM 7% 10% Logic 12% 24%

From table 1 the problem is evident, from 250nm to 130nm processes the mask cost for an ASIC design has risen from an already high 32% to 56% of the cost of the wafer! For a complex 130nm foundry process such as TSMC offers with 8 layers of copper we estimate the mask set cost at $814 thousand dollars and at 90nm the cost will exceed $1 million dollars. Even logic processes with 1,500 mask uses per wafer have reached mask costs of 24% of the total wafer cost.

Mask set costs clearly represent a huge issue for low volume ASIC designers in terms of product cost. The cost of the mask set also places a huge barrier in front of designers with first pass success becoming essential.