Chartered anounces 20% utitilization, how bad is that?
Introduction
Actually... it's really bad. If we assume 200mm wafers and a 250nm CMOS logic process with 6 layers of aluminum and a toolset that is 85% depreciated, then from the 2001 IC Cost Model at 20% utilization we calculate a wafer cost of $3,463. Contrast this to current average foundry pricing of $1,958 to $1,857 (source: FSA) for the same wafer and a wafer cost of $1,127 at a 95% utilization such as was common 12 months ago, and what could have been a 39% gross margin becomes a negative 86% gross margin.
